easyDSP uses 'UART'
boot mode for RAM booting and flash programming, and uses
'QSPI(4S) - Quad Read Mode' boot to run user program in the flash.
Boot Mode |
SOP3 | SOP2 | SOP1 | SOP0 |
QSPI (4S) - Quad Read Mode |
0 | 0 |
0 |
0 |
|
UART |
0 |
0 |
0 |
1 |
|
QSPI (1S) - Single Read Mode |
0 |
0 |
1 |
0 |
|
QSPI (4S) - Quad Read UART Fallback Mode |
0 |
1 |
0 |
0 |
|
QSPI (1S) - Single Read UART Fallback Mode |
0 |
1 |
0 |
1 |
|
DevBoot |
1 |
0 |
1 |
1 |
According
to the table above, SOP1, SOP2 and SOP3 pins should be low while
SOP0 pin is connected to BOOT pin of easyDSP header so that easyDSP can
control MCU boot mode.
It is highly recommended to
connect RX and TX pins of easyDSP header to MCU UART0 (MUXMODE 0). Otherwise
RAM booting and flash programming is not supported.
In case RX and TX pins of
easyDSP header are connected to UART other than UART0 (MUXMODE 0), don't connect BOOT and
/RESET pin of easyDSP header.
The flash should be connected to MCU QSPI0
and its 'Sector Erase' command should work with 64kB block such as part
number S25FL128SAGNFI000 which is used in TI evaluation
board.
#4 pin of easyDSP header is
connected to MCU VDDS33.
Note :
- 25MHz XTAL clock source
is required.
-
MCU captures SOPx pin status ~1ms after PORz release and decides boot
mode. So, kindly make sure there would be no signal output from any circuitry connected to
SOPx pin ~2ms after PORz release.
- TX and RX pin of easyDSP header is pulled up
with 100k Ohm resistor inside of easyDSP pod.
- In case there is a reset IC between
easyDSP /RESET and MCU PORz, it should transfer easyDSP /RESET signal to
MCU within 0.5sec.
